32-bit RISC IP, High-Performance CPU

Our eSi-3250 32-bit RISC IP core is a high-performance processor ideal for integration into ASIC and/or FPGA designs with off-chip memories.  The eSi-3250 CPU is suited to a wide range of applications including running complex operating systems such as Linux.

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32-bit RISC IP: eSi-3250 Technical Overview

  • Features

    • 32-bit RISC architecture
    • 16 or 32 general purpose registers
    • 104 basic instructions and 10 addressing modes
    • Optional IEEE 754 floating point unit (FPU)
    • Supports up to 90 user-defined instructions
    • 5-stage pipeline
    • Optional memory management unit (MMU)
    • Configurable instruction and data caches (1-64kB, direct mapped or 2 or 4 way associative)
    • AMBA AXI or AHB interconnect and APB peripheral bus
    • User and supervisor modes
    • Up to 32 vectored interrupts plus NMI and system call
    • HW nested and prioritizable interrupts
    • Fast interrupt response time of 6-9 cycles
    • JTAG or serial debug, with optional trace
    • Up to 4.12 CoreMark per MHz
    • Intermixed 16 and 32-bit instructions result in exceptional code density without compromising performance
    • ASIC performance (Typical 90nm):
      • Up to 700 MHz
      • From 20k gates
      • From 22uW/MHz
    • FPGA Performance (Stratix IV):
      • Up to 200 MHz
      • From 2200 ALUTs
    • High quality IP:
      • Verilog RTL
      • DFT ready
      • Silicon proven
    • C and C++ software development using license-free toolchain, under industry standard Eclipse IDE
    • Easy migration path to cacheless version
  • Applications

    • Consumer
    • Industrial control
    • Medical
    • Communications
    • General purpose
  • Architecture

    The eSi-3250 32-bit CPU is targeted specifically for applications with high performance and large memory requirements.

    The processor features separate instruction and data caches that can be configured in size (from 1- 64kB) and associativity (direct mapped, 2 or 4-way associative) to increase performance when accessing off-chip memory. The optional paged memory management unit (MMU) enables the implementation of virtual memory and the ability to run operating systems such as Linux.

    The 5-stage pipeline allows extremely high clock frequencies to be achieved.

    The eSi-3250’s instruction set includes everything you would expect in a high-performance processor. There are also a number of optional application specific instructions and addressing modes. For example, a set of IEEE-754 compliant single and double precision floating point instructions are available. Bit manipulation instructions such as bitfield extract and insert, count leading zeros, population count, find first set and bit reverse are available. Integer square root, absolute value, min/max, CRC and parity can also be included in a core.

    For those applications that require extreme performance or ultra low power operation, user-defined instructions and registers can be implemented.

    Instructions are encoded in either 16 or 32-bits, with all of the commonly used instructions being encoded in 16-bits, maximizing code density and improving cache performance.

    The processor supports both user and supervisor operating modes, with privileged instructions and memory areas, to allow an O/S kernel to be fully protected from user applications.

    Hardware debug facilities include hardware breakpoints, watchpoints, trace, null pointer detection and single stepping for fast debugging of ROM, FLASH and RAM based programs.

  • Toolchain

    RISC2The toolchain is based upon the industry standard GNU toolchain, which includes an optimising C and C++ compiler, assembler, linker, debugger, simulator and binary utilities. All these tools can be driven by the customisable Eclipse IDE or from the command line.

    The debugger can connect to HW targets via a low cost USB-JTAG adaptor and RTL simulation via a Verilog PLI library.

    Complete C and C++ libraries are supplied. Ports of Micrium’s uC/OS-II RTOS, ThreadX, FreeRTOS and the lwIP TCP/IP stack are available. The toolchain is available for both Windows and Linux hosts and is available to use at no additional cost.

  • IP Delivery

    The eSi-3250 is delivered as a Verilog RTL IP core. The design is target technology independent and DFT ready, supporting full scan insertion for all flip flops and memory BIST. Example scripts are provided for popular EDA tools.

    A selection of AMBA peripherals can be supplied with the core, including: UART, SPI, I2C™, I2S, Timer, PWM, Watchdog, GPIO, PS/2, RTC, Ethernet MAC, USB, FIFO, Scatter-Gather DMA, AES, SHA, ECC and a quad-SPI Flash interface. By using an industry standard bus, a wide range of 3rd party IP cores are compatible with the eSi-3250.

    eSi-RISC can generate a multilayer AHB matrix and APB bus to connect the eSi-3250 CPU, memory and peripherals, according to a customer’s specification.