16-bit RISC Processor – Low-Cost & Low-Power CPU

Our eSi-1600 16-bit RISC CPU IP core is an extremely small, low-cost and low-power processor ideal for integration into ASIC and/or FPGA designs. It offers similar performance to more expensive 32-bit CPUs, while having a system cost comparable to that of 8-bit CPUs. Significant power savings are possible compared to 8-bit CPUs as applications require far fewer clock cycles to run.

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  • Features

    • 16-bit RISC architecture
    • 16 general purpose registers
    • 92 basic instructions and 10 addressing modes
    • Supports up to 90 user-defined instructions
    • 5-stage pipeline
    • AMBA AHB and APB peripheral bus
    • Optional support for user and supervisor modes
    • Up to 16 vectored interrupts plus NMI and system call
    • HW nested and prioritizable interrupts
    • Fast interrupt response time of 6-9 cycles
    • JTAG or serial debug, with optional trace
    • Up to 2.81 CoreMark per MHz
    • Multiprocessor support
    • High code density
    • ASIC performance (Typical 0.13um):
      • Up to 600 MHz
      • From 8.5k gates
      • From 15uW/MHz
    • FPGA Performance (Virtex 5):
      • Up to 160 MHz
      • From 1100 LUTs
    • High quality IP:
      • Verilog RTL
      • DFT ready
      • Silicon proven
    • C and C++ software development using license-free toolchain, under industry standard Eclipse IDE
    • Easy migration path to 32-bit version
  • Applications

    • Home automation
    • Industrial control
    • Medical
    • Low-power wireless
    • Data communication
    • Power management
  • Architecture

    The eSi-1600 16-bit CPU is the smallest member in the eSi-RISC family of processor cores from EnSilica. It is targeted specifically for low-cost and low-power applications, where typically an 8-bit CPU may have previously been used, or where a 32-bit CPU is too big or power hungry. Even though it is 16-bit, the gate count is equivalent to many 8-bit cores due to the simplicity of the RISC pipeline.

    With a wider datapath and 16 general purpose registers, application programs are able to execute in far fewer clock cycles. This can save a significant amount of power by either allowing the CPU to be clocked at a lower frequency or by being able to enter a power down state sooner.

    For applications where high performance is required, the 5-stage pipeline allows extremely high clock frequencies to be achieved. The optimising C/C++ compiler is fully aware of the pipeline and is able to schedule instructions to eliminate latencies.

    The eSi-1600’s instruction set includes arithmetic and logical instructions (including barrel shift, multiply and divide), comparisons, load and stores, branches and calls as well as system level instructions to control interrupts and enter lower power states. Bit manipulation instructions such as bitfield extract and insert, count leading zeros, population count, find first set and bit reverse are available. Integer square root, absolute value, min/max, CRC and parity can also be included in a core.

    There are also a number of optional instructions and addressing modes that can be selected, should a specific application require them. For those applications that require extreme performance or ultra low power, user defined instructions and registers can be implemented.

    Hardware debug facilities include hardware breakpoints, watchpoints, trace, null pointer detection and single stepping for fast debugging of ROM, FLASH and RAM based programs.

  • Toolchain

    The toolchain is based upon the industry standard GNU toolchain, which includes an optimising C and C++ compiler, assembler, linker, debugger, simulator and binary utilities. All these tools can be driven by the customisable Eclipse IDE or from the command line.

    The debugger can connect to HW targets via a low cost USB-JTAG adapator and RTL simulation via a Verilog PLI library.

    Complete C and C++ libraries are supplied. Ports of Micrium’s uC/OS-II RTOS, ThreadX, FreeRTOS and the lwIP TCP/IP stack are available. The toolchain is available for both Windows and Linux hosts and is available to use at no additional cost.

  • IP Delivery

    The eSi-1600 is delivered as a Verilog RTL IP core. The design is target technology independent. The design is DFT ready, supporting full scan insertion for all flip flops and memory BIST. Example scripts are provided for popular EDA tools.

    A selection of AMBA peripherals can be supplied with the core, including: UART, SPI, I2C™, I2S, Timer, PWM, Watchdog, GPIO, PS/2, RTC, Ethernet MAC, USB, FIFO, Scatter-Gather DMA, AES, SHA, ECC and a quad-SPI Flash interface. By using an industry standard bus, a wide range of 3rd party IP cores are compatible with the eSi-1600.

    eSi-RISC can generate a multilayer AHB matrix and APB bus to connect the eSi-1600 CPU, memory and peripherals, according to a customer’s specification.