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eSi-RISC Processor IP

Configurable Embedded RISC Processor IP

eSi-RISC is a highly configurable microprocessor architecture for embedded systems, that scales across a wide range of applications.

The eSi-RISC IP core has been silicon proven in a wide range of ASIC and FPGA technologies, from 0.35um to 16nm FinFET.

  • Configurable 16 or 32-bit, 5-stage pipelined RISC, load-store architecture.
  • Implemented in as little as 8k ASIC gates for minimum 16-bit configuration.
  • Intermixed 16 and 32-bit instructions gives exceptional code density.
  • Uses industry standard bus architecture for IP interconnection (AMBA AXI/AHB/APB).
  • Multiprocessor, SIMD and floating-point options.
  • Configurability and custom instructions will deliver a solution with exceptionally low-power.
  • Supports user and supervisor modes and HW nested interrupts.
  • JTAG or serial hardware debug, with optional trace.
  • Up to 4.12 CoreMark per MHz.


eSi-RISC SoC

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eSi-RISC Product Family

eSi-1600

The eSi-1600 16-bit CPU core is a low-cost, low-power processor. It offers similar performance to more expensive 32-bit CPUs while having a system cost comparable to that of 8-bit CPUs. It is ideally suited for control applications in mature mixed-signal processes, requiring less than 64kB of memory.

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eSi-1650

The eSi-1650 16-bit CPU core is a small, low-power processor that includes an instruction cache. The cache provides a very power and area efficient solution for mature process nodes using OTP or Flash for program memory. It avoids the need for large on-chip shadow RAMs, whilst allowing the CPU to run at its maximum frequency, rather than be limited to the OTP/Flash frequency.

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eSi-3200

The cacheless eSi-3200 32-bit core, is a small, low-power CPU for embedded control applications.  The configurable instruction set includes a vast range of instructions such as a 64-bit multiply-accumulate as well as a fixed-point complex multiply with rounding for FFTs and FIRs. It can also support 32-bit SIMD and single-precision floating point, as well as power management instructions.

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eSi-3250

eSi-RISC’s eSi-3250 32-bit RISC IP core is a high-performance processor ideal for integration into ASIC and/or FPGA designs requiring instruction and data caches, due to the use of slow on-chip memories such as eFlash, off-chip memories, or where the CPU core to bus clock ratio is greater than 1. The eSi-3250 also supports an MMU with address translation, and like all eSi-RISC processors, the ability to add user-defined custom instructions.

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eSi-3264

eSi-RISC’s eSi-3264 32/64-bit CPU includes 64-bit fixed and floating-point SIMD (Single Instruction Multiple Data) DSP extensions as well as double-precision floating-point. It is targeted specifically for applications needing DSP functionality with minimal silicon area. It has the largest instruction set of all eSi-RISC processors, including specialist instructions for a wide variety of applications.

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eSi-RISC IP Technical Overview

  • Benefits

    • Highly configurable, allowing the processor to be tailored to fit a wide range of applications, on both FPGA and ASIC technology.
    • Performance and code density amongst the very best available.
    • Silicon proven in multiple production devices, from 0.35um to 16nm FinFET.
    • License-free professional development suite using Eclipse IDE and GNU tools.
    • Delivered as fully integrated CPU sub-system with peripherals and memory to shorten time to market.
    • High quality support and documentation.

  • Scalabilty

    All of the eSi-RISC processors share a common RTL database and software toolchain, resulting in an easy migration path for both software and hardware developers, should the demands of an application change.

  • IP Delivery

    The eSi-RISC is implemented as a soft IP core, based on synthesisable Verilog RTL and can be easily ported to a wide range of ASIC processes and FPGAs. The design is DFT ready, supporting full scan insertion for all flip flops and memory BIST.

    A selection of AMBA peripherals are supplied with the core, including: UART, SPI, I2C™, Timer, PWM, Watchdog, GPIO, PS/2, Ethernet MAC as well as a static memory interface and DMA engine. By using an industry standard bus, a wide range of 3rd party IP cores can also be used.

  • Toolchain

    The toolchain is based upon the industry standard GNU toolchain, which includes an optimising C and C++ compiler, assembler, linker, debugger, simulator and binary utilities. All these tools can be driven by the customisable Eclipse IDE (Integrated Development Environment). The toolchain is available for both Windows, Linux and macOS hosts and is available to use at no additional cost.

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  • Development Kit

    A hardware development kit is available for evaluating these cores. This board provides a range of memory and external interfaces to suit most applications.

  • Support

    By utilising eSi-RISC’s system level design expertise to define the most appropriate configuration for your particular application and then using our design services to integrate the eSi-RISC core within your particular design, you can achieve a truly optimised solution without any of the pain often associated with embedded processor designs.