eSi-1650

16-bit RISC IP, Low-Cost & Low-Power CPU with Cache

Our eSi-1650 16-bit CPU IP core is an extremely small, low-power processor with an instruction cache. The low gate count and cache feature provides a very power and area efficient solution for mature process nodes using OTP or Flash for program memory.

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16 bit RISC IP: eSi-1650 Technical Overview

  • Features

    • 16-bit RISC architecture
    • 16 or 32 general purpose registers
    • 92 basic instructions and 10 addressing modes
    • Supports up to 90 user-defined instructions
    • 5-stage pipeline
    • Instruction cache
    • AMBA AHB and APB peripheral bus
    • Optional support for user and supervisor modes
    • Up to 16 vectored interrupts plus NMI and system call
    • HW nested and prioritizable interrupts
    • Fast interrupt response time of 6-9 cycles
    • JTAG or serial debug, with optional trace
    • Up to  2.81 CoreMark per MHz
    • Multiprocessor support
    • High code density
    • ASIC performance (Typical 0.13um):
      • Up to 600 MHz
      • From 8.5k gates
      • From 15uW/MHz
    • FPGA Performance (Virtex 5):
      • Up to 160 MHz
      • From 1100 LUTs
    • High quality IP:
      • Verilog RTL
      • DFT ready
      • Silicon proven
    • C and C++ software development using license-free toolchain, under industry standard Eclipse IDE
    • Easy migration path to 32-bit version
  • Applications

    • Touch screen controllers
    • Smart sensors for IoT
    • Home automation
    • Industrial control
    • Medical
    • Low-power wireless
    • Data communication
    • Power management
  • Architecture

    The eSi-1650 16-bit CPU with instruction cache is targeted specifically for low-cost and low-power applications, where typically an 8-bit CPU may have previously been used or where a 32-bit CPU is too big or power hungry. The instruction cache provides a high performance, area and power efficient solution when running from on-chip NVM or Flash.

    The use of the cache allows higher CPU frequencies when in mature technologies as frequency is typically limited by the memory speed.

    Even though it is 16-bit, the gate count is equivalent to many 8-bit cores due to the simplicity of the RISC pipeline. With a wider datapath and 16 general purpose registers, application programs are able to execute in far fewer clock cycles. This can save a significant amount of power by either allowing the CPU to be clocked at a lower frequency or by being able to enter a power down state sooner.

    or applications where high performance is required, the 5-stage pipeline allows extremely high clock frequencies to be achieved. The optimising C/C++ compiler is fully aware of the pipeline and is able to schedule instructions to eliminate
    latencies.

    The instruction set includes arithmetic and logical
    instructions (including barrel-shift, multiply and divide), comparisons, load and stores, branches and calls as well as system level instructions to control interrupts and enter lower power states. Bit manipulation instructions such as bitfield extract and insert, count leading zeros, population count, find first set and bit reverse are available. Integer square root, absolute value, min/max, CRC and parity can also be optionally included in a core.

    For those applications that require extreme performance or ultra low power, user-defined instructions and registers can be implemented.

    Hardware debug facilities include hardware breakpoints, watchpoints, trace, null pointer detection and singlestepping for fast debugging of ROM, FLASH and RAM based programs.

  • Toolchain

    RISC2

    The toolchain is based upon the industry standard GNU toolchain, which includes an optimising C and C++ compiler, assembler, linker, debugger, simulator and binary utilities. All these tools can be driven by the customisable Eclipse IDE or from the command line.

    The debugger can connect to HW targets via a low cost USB-JTAG adapator and RTL simulation via a Verilog PLI library.

    Complete C and C++ libraries are supplied. Ports of Micrium’s uC/OS-II RTOS, ThreadX, FreeRTOS and the lwIP TCP/IP stack are available. The toolchain is available for both Windows and Linux hosts and is available to use at no additional cost.

  • IP Delivery

    The eSi-1650 is delivered as a Verilog RTL IP core. The design is target technology independent and DFT ready, supporting full scan insertion for all flip flops and memory BIST. Example scripts are provided for popular EDA tools.

    A selection of AMBA peripherals can be supplied with the core, including: UART, SPI, I2C™, I2S, Timer, PWM, Watchdog, GPIO, PS/2, RTC, Ethernet MAC, USB, FIFO, Scatter-Gather DMA, AES, SHA, ECC and a quad-SPI Flash interface. By using an industry standard bus, a wide range of 3rd party IP cores are compatible with the eSi-1650.

    eSi-RISC can generate a multilayer AHB matrix and APB bus to connect the eSi-1650 CPU, memory and peripherals, according to a customer’s specification.