The eSi-Connect IP suite is a comprehensive range of processor peripherals each with standard AMBA AHB or AHB interfaces to simplify SoC integration and connectivity.

The portfolio includes memory controllers (SMI, DDR, SPI Flash) as well as widely used off-chip interfaces such as USB, I2C, SPI and UART and control functions including Timer, Real-time Clock, Watchdog and GPIO. The blocks are configurable and provided with low-level software drivers suitable for real-time SoC deployment.

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esi-Connect: AMBA Peripheral IP Technical Overview


eSi-SPI is an APB Serial Peripheral Interface (SPI). It uses a 4-wire serial bus to implement full-duplex, synchronous, serial communications. The core is software programmable and includes configurability for word size (1 or 32-bits), bit ordering (MSB first / LSB first), clock polarity and phase as well as bit rate. It supports both master and slave modes. Chip-select generation can be automatic or manual and multiple chip-select outputs are supported. TX and RF FIFO sizes are configurable. Auto TX and RX modes are available to reduce APB bus bandwidth requirements.


The I2C slave and master is a 2-wire serial bus interface typically used to control peripherals requiring a low speed and limited control interface, for example an EEPROM. This module supports 100kbps and 400kbps I2C modes as well as 7 and 10-bit addressing and clock stretching.


The eSi-UART core can be used to implement asynchronous serial communications. It is ideally suited for implementing RS232 or ISO7816-3 for smartcard based connectivity. It supports a wide range of software configurable UART settings including 7 or 8 bit data, 1 or 2 stop bits and parity. The module supports ISO7816-3 modes T=0 and T=1 with hardware NACK and retry functionality.


The eSi SG-DMA core can be used to implement 1D and 2D memory-to-memory, memory-to-peripheral, peripheral-to-memory and peripheral-to-peripheral block data transfers, with scatter-gather functionality.

It supports a configurable number of channels and number of peripherals. Transfer descriptors are memory-based and include linked-list elements for chaining of descriptors. 3 descriptor sizes balance functionality and overhead. The full descriptor includes programmable X and Y count, increment, access size and burst length. Optional CRC and IP checksum calculation is supported. Dual AHB-lie master interfaces allow for  simultaneous read and write.

eSi-SPI Flash

The eSi-SPI Flash core can be used to provide both a memory mapped interface and control register based interface to a serial flash memory device. It has Execute-in-place (XIP) support to allow code to execute directly from flash Programmable bit rate. It also supports serial, dual and quad-mode SPI flash devices, auto-incrementing addresses (saves transmitting sequential addresses), I/O mode (transmits address in dual/quad mode as well as data) and continuous mode (saves transmitting read commands)


The eSi-SMI core provides a static memory interface, allowing access to off-chip RAM, ROM and FLASH memory devices. It supports a configurable number of data (8/16/32) and address pins and configurable number of banks (1-8). Each bank has programmable settings, including: data width, wait states, write-protect and privilege-level.


The eSi-GPIO is a fully featured GPIO controller. The IP provides bi-directional inputs and outputs, plus optional level/edge detection of each input for generating interrupts and pull-up/down control logic.


The eSi-EMAC core implements an Ethernet Media Access Controller (MAC), providing access to 10/100Mbps Ethernet networks. It is a highly compact design featuring low gate count and low power making it ideally suited for providing network connectivity to 16 or 32-bit MCUs via an AMBA APB interface.

eSi-TSMC Flash

The eSi-TSMC Flash core provides an interface a TSMC embedded flash. It supports access to both data memory and information memory blocks. It has optional ECC support with SECDEC (single-bit error correction, double-bit error detection). Programmable read/write timings support varying clock frequencies.


The eSi-Watchdog core can be used to generate an interrupt if a keep-alive sequence is not written to its control registers at a regular interval. This would typically be used to determine whether a program is running correctly, on the assumption that a program that has crashed would not write the correct sequence. The interrupt output would typically drive either the reset or non-maskable interrupt on the CPU, to restart the program.


The eSi-PWM is a pulse width modulation waveform generator. Features include a configurable number of PWM channels, runtime programmable duty cycle from 0% to 100% and configurable period.

eSi-Multichannel Timer

The eSi-Multichannel Timer is a low gate count multichannel timer. It has the following features: configurable number of channels, counter width and single-shot or continuous mode of operation.


eSi-Timer is a software programmable multi-function timer/counter used for system timing functions.


eSi-PS/2 is a PS/2 host interface to communicate with devices such as keyboards and mice.


The eSi-I2S core is a high quality implementation of an I2S interface using a standard AMBA AHB bus interface. It can be used to transmit and receive audio data via the I2S protocol.


The eSi-FIFO core can be used to implement a FIFO between two AHB buses or masters. Its main features are; Configurable FIFO width and depth , Programmable almost full and almost empty interrupts , Overflow and underflow protection , Dual AMBA 3 AHB-lite slave interface for FIFO and control register access.


The eSi-CRC core is used to calculate cyclic redundancy check (CRC) values for blocks of data. It supports; Programmable CRC polynomial, Integrated DMA – zero CPU overhead, supporting: CRC-32, CRC-32C, CRC-16, CRC-16-CCITT and CRC-8 as well as others,  AMBA 3 AHB-lite slave/master interface for control register access/ for data transfers respectively.