Delta Microelectronics

DELTA’s design team developed a low-power ASIC for a wireless tag application using the eSi-3200 32-bit processor IP core. The integration process was very smooth, with an excellent set of deliverables, documentation and examples. We had the processor core integrated with our own peripheral IP very quickly. The tools and debug facilities were very professional including support for both Linux and Windows, there were some excellent features to support hardware and software co-simulation which reduce the overall verification cycle.

“DELTA and our end customer are very pleased with the quality of the IP and the overall power saving it delivered over using other cores, we will certainly use it on other projects requiring a low-power, silicon efficient MCU.”

Per Ølund
Executive Vice President
Detla Microelectronics

Dongbu Hitek

Dongbu Hitek

At the start of our new project, there were several candidate CPUs for this product. After an extensive technical and commercial evaluation Dongbu HiTek selected the eSi-1600 processor IP and peripherals set for our project.

While evaluating their IP, eSi-RISC’s team responded fast and professionally and had all the relevant experiences to support our project. Even though there is no local office in Korea, they supported in real time.

They understood our project requirements and we found the IP had very competitive performance. During developing our project, the support team proposed some custom instruction specific to our application that saved important memory and power.

Their quality IP and support made our project on-time and a success. Through silicon verification, there was no CPU issue found and we were very pleased with the result.

We have decided to use their IP for our next project and we are confident that eSi-RISC will again provide the best service and support to make this another success project.

Haejin Song
Dongbu HiTek

Kili Corporation

Kili Corp

My team has been working with eSi-RISC for a number of years over a number of IC developments, and the level of service and quality of the IP they provide is excellent. During the processor evaluation, eSi-RISC’s level of support was excellent. We were able to demonstrate that the configurability and custom instructions provided us with real technical differentiation compared to other CPU cores.

As part of the license agreement, eSi-RISC also provided a design services package to deliver a complete multi-processor AMBA sub-systems including cache memory, USB and all the key peripherals required for our application. This included external APB buses to allow us to connect our own IPs. The delivery came complete with software API and examples allowing us to quickly implement our own application code on an FPGA platform in parallel with the chip development.

During the process we requested a number of changes to the system which were turned around very quickly and efficiently. Outsourcing the processor sub-system to eSi-RISC helped reduce our IC development time and allowed us to focus on our end application specific IPs and differentiation. The flexible multi-processor architecture has helped us developed novel security features to meet FIPS security certification.

We plan to continue to use IP’s from eSi-RISC in future products and will use their services to support our ongoing chip development activities.

Kili Corporation, Toronto, Canada
Afshin Rezayee
Founder and Co-President

Xtendwave

xtendwave

Xtendwave licensed eSi-3200 32-bit processor core to power our EverSet® time code receiver solution for decoding the WWVB atomic timekeeping signal. The processor IP came fully integrated with a complete set of peripherals, memories for our chosen technology and external interfaces to connect our own IPs. eSi-RISC provided Xtendwave with a version of eSi-3200 optimized for the EverSet® application, configuring it to reduce the overall processor gate count significantly compared to the competing solution. The optimized version also featured custom trigonometric instructions reducing cycle count by 30% and a 2Kbyte reduction in valuable memory space.

eSi-RISC also provided additional services including full RTL to GDSII development services and development of scan vectors and software for memory testing and BIST to support our IC production. The services were delivered to schedule and budget and always to a high quality. eSi-RISC’s team was easy to work with and provided us with the expertise and skills we needed to get a quality solution in a very short timeframe. We would recommend eSi-RISC to any fabless semiconductor company looking to accelerate their chip development.

Tom Jung
Senior Design Engineer
Xtendwave

novelIC

In our projects we pick eSi-RISC cores when we need good hardware performance and a highly configurable RISC IP. We particularly value the feature richness and the custom opcode extensions, so that we could include our custom hardware accelerators. Nice and clean RTL code is very valued by our SoC architects. Support is given by very knowledgeable and kind colleagues, which we appreciate the most.

Veljko Mihajlovic
CTO
NovelIC

Cirque Corporation

Cirque is in a very competitive, high volume consumer electronics market space. We have been shipping computer touchpad controller chips since 1991.

We recently wanted to update one of our touch controller chips to enhance several analog and digital features and to reduce the cost. Three months before we planned on finalizing the digital design, we learned of an open source, royalty free 32-bit RISC CPU core called RISC-V. Our current CPU core choice worked fine, but the toolchain was unsupported, and the royalties were too high for our market space. This new CPU core option looked very attractive, but it wasn’t quite a drop-in replacement for the current core. This RISC-V core also didn’t have some of the peripherals needed, including timers and UART. Changing the CPU core in an ASIC is typically a big commitment and has a considerable impact on system performance, including firmware code development. We decided to spend 2 weeks shopping for other CPU core options that might be a better fit for our application.

We quickly found a wide range of eSi-RISC CPU cores on eSi-RISC website. These cores had very competitive specs and came with all the other peripherals we needed. Their website was easy to navigate and contained all of the information we needed without requiring an NDA to access it.

We considered other CPU vendors, but we found that their websites did not provide adequate information. To obtain information from these vendors we were required to secure NDAs and multiple email communications. This led to significant delays in gathering the needed comparative data for us to make a decision.

This chip revision had a very aggressive design cycle. Because of this, one of our primary requirements for replacing the CPU core was that it needed to be a near drop-in replacement. The current CPU core and in-house peripherals used a non-standard peripheral bus which was not available with the eSi-RISC core. After describing this issue and the peripheral bus function to the eSi-RISC’s engineering team, they were able to generate a peripheral bus conversion module and delivered a full RTL package for us to evaluate in one day, including the peripherals that we needed and all of the customized parameters that were required for our design. eSi-RISC did not require additional NDA agreements to get the evaluation, which saved precious time.

Some of the eSi-RISC cores have optional cache memories. This was very intriguing, but we weren’t sure how much added performance it would provide our design. eSi-RISC suggested we try it out and we could easily remove the option if it wasn’t needed. They provided the cache option in the evaluation RTL so that we could run simulations and synthesis to see if it was a good fit for us. In the end, we decided not to use the cache, but we were impressed by how quickly they responded to changing parameters.

During the integration and verification, we had a number of questions and debug issues that came up. We were very pleased with the responsiveness of the eSi-RISC support team. Whenever we emailed questions, no matter the time of day, we almost always got an immediate response and most of the time with a concise and complete answer.

We planned on having 2 of our engineers do the integration and verification, but one was predisposed on another project for almost the entire 2 months. The eSi-RISC RTL was easy enough to read and to debug that, along with the help of one of their support engineer, we met our digital completion schedule with only one engineer on a tight deadline.

The eSi-RISC core was very attractive for many reasons:
· No royalty payments
· Low instance cost
· Flexible architecture made it a near drop-in replacement of our previous CPU core
· Impressive performance specs
· Low gate count
· Came with the peripherals we needed
· Excellent upfront sales documentation that answered all the competitive and integration questions
· Very good implementation guides and user guides
· Excellent technical support based in the UK
· Easy to read RTL
· Test bench modules that make debugging easy

We have been very happy with all aspects of the eSi-RISC cores and we highly recommend them

Jared Bytheway
R&D Manager
Cirque Corporation
April 2019

Posedge

Posedge

To support our innovative wired packet processor sub-system IP, Posedge required multiple instantiations of an embedded processor with 3 different configurations. Due to the number of cores in the system the key selection criteria was a low gate-count and good code density as well as the requirement to support multi-core debug.

Of three processors evaluated, only the eSi-3250 exhibited the combination of functionality and flexible licensing that we needed to take our product development plans forward. eSi-RISC even created a special version of the eSi-3250, with the option to switch the caching capability on and off, giving us extra flexibility.

The eSi-3250 is also backed by a professional toolchain capable of supporting multi-core debug and validation. We used both the Windows and Linux version that are both easy to use and very stable. Posedge are now standardising on the eSi-3250 for all our wired/wireless networking IP solutions.

eSi-RISC have provided excellent support to our USA and Indian based teams through the complete design cycle as well as during silicon bring-up.

Chakra Parvathaneni
Vice-President of Marketing
Posedge Inc

Semisens

testimonial-semisens-logo

Semisens could reduce die size and lower power consumption of our touch screen controllers usingIP’s of eSi-RISC. Those devices are now successfully released to the market. Benchmarking performed by one of end customers showed that Semisens touch controller consumes lowest power among touch controllers available in the market. In addition to the value the CPU core, eSi-RISC’s IP provides ease of integration and verification with other logic blocks. Quick application support of quality apps engineers also made our IC design engineers feel comfortable to work with eSi-RISC. With all those benefits brought to our chip design, eSi-RISC is now selected as the sole CPU vendor for Semisens. We are glad that the right partnership made our device achieve the best performance and the highest value in this competitive market.

Dave Lee
SoC Design Manager

Solantro

Solantro

After an extensive search, we found eSi1600/3200 to be an excellent match for our controller IP requirements. We were very pleased with the quality of the code and the documentation. Technical support was perfect during the entire engagement, always prompt and relevant. The ASIC implementation of the core performed as expected in the first tape-out. As an early-phase start-up with a tight R&D budget, Solantro benefitted from an excellent technical and business partnership with eSi-RISC, allowing us to move to the next level.

Christian Cojocaru
Director IC Engineering
Solantro Semiconductor Corp.

Solomon Systech

Solomon Systech

The solution developed by eSi-RISC, with its excellent features, has enhanced greatly the functionality of our product. We look forward to joining hands again with the team to develop more high-performance IC solutions

Ken Tsui
Vice PresidentDesign Engineering
Solomon Systech Limited.

L&T Technology Services

Out team at LnT used a dual processor systems with the eSi-3260 from a data processing intensive applications. As well as the processor eSi-RISC provided much of the peripheral IP, cryptographic accelerator and bus interconnection IPs all integrated together to our requirements. The delivery was of high quality and allowed us to integrate other 3rd party IP and our own USB IP very quickly into the processor sub-systems provided. We had our first an FPGA prototype systems running in a matter of days. The tools were all GNU based and very professional and the support we received was of a very high standard. We will certainly look to use the IP again on other projects.

Jos Sebastian
Sr. Director and Head of VLSI IPs
L&T Technology Services