As part of our ongoing expansion, EnSilica are looking to strengthen our verification team. We are looking for bright candidates who have an enthusiasm and aptitude for taking on the most challenging verification projects.
You will have a broad understanding of different methodologies, but particularly SystemVerilog and OVM/UVM. Faced with a new project, you will have the ability to develop an effective (and pragmatic) verification strategy and gain the support of the end-customer for the chosen approach.
You will be comfortable taking on the role of verification lead, architecting the test environment and driving the other team members to deliver the agreed solution. You understand the importance of monitoring key metrics to assess progress and predict the end-point for the verification process.
With 5+ years experience in industry you will relish the opportunity of working on a diverse range of projects that will both challenge and develop your verification skills.
Ideally you will be familiar with both Mentor Questa and Cadence Incisive tools.
The candidate should have customer facing experience and excellent communication skills.
Key tasks / responsibilities :
• Verification specialist working on customer projects – sometimes as the verification lead.
• To support business development by working with potential customers to understand their verification requirements and develop innovative technical solutions to achieve the design win
• Provide high-class verification support to a wide range of projects. Key tasks would include :
o Development of a comprehensive verification strategy and plan
o Architecting and development of the complete test environment
o Generation of tests to achieve required functional coverage
• Active participation in the Verification community to drive the introduction of new and effective techniques within our business
• Close working with Customer
Key skills / Background :
• 1st or 2.1 Electronics, Physics or Computer Science from a Tier 1 group University
• 5+ years experience in industry working on a variety of verification projects
• Extensive knowledge of verification methodologies particularly OVM/UVM and SystemVerilog
• Strong experience in the specification and implementation of verification infrastructures, test benches, models, assertions and functional tests in Verilog and SystemVerilog.
• Familiarity with constrained random verification methodologies, code coverage analysis and running regression tests
• Strong VHDL/Verilog RTL
• Good customer facing skills
Personal skills :
• Excellent communication and interpersonal skills
• Strong and effective presentation skills, able to operate at multiple levels including senior management
• Self motivated
• Take ownership of problems
• Creative problem solving
• Team player
No agencies please.